In the related art, amplification type solid-state imaging devices represented by metal oxide semiconductor (MOS) type image sensors such as complementary metal oxide semiconductors (CMOSs) are known as solid-state imaging devices. Also, charge transfer type solid-state imaging devices represented by charge coupled device (CCD) image sensors are known.
Solid-state imaging devices have been widely used for digital still cameras, digital video cameras, or the like. In recent years, MOS type image sensors have been used as solid-state imaging devices mounted on mobile devices such as mobile phones with cameras, personal digital assistants (PDAs), and the like in many cases due to a low power voltage, a viewpoint of power consumption, or the like.
An MOS type solid-state imaging device is formed by a photodiode (PD) in which a unit pixel is a photoelectric conversion part and a plurality of pixel transistors, and is constituted by a pixel array (a pixel region) in which the plurality of unit pixels are arranged two-dimensionally and a peripheral circuit region. The plurality of pixel transistors are formed by MOS transistors and are constituted by 3 transistors which have a transfer transistor, a reset transistor, and an amplifier and transistor or 4 transistors in which a selection transistor is added to the 3 transistors.
Also, in the above-described solid-state imaging device, a stacked structure in which a plurality of semiconductor chips having different functions overlap each other to be electrically connected to each other has also been proposed.
Since circuits can be optimally formed to correspond to functions of semiconductor chips in a stacked structure, a high functionality of a device can be easily realized.
For example, a sensor circuit and a logic circuit are optimally formed to correspond to functions of a semiconductor chip provided with a sensor circuit and a semiconductor chip provided with a logic circuit in which a circuit configured to process a signal is provided so that a high-performance solid-state imaging device can be manufactured. In this case, through electrodes are provided in substrates of the semiconductor chips to electrically connect a plurality of semiconductor chips to each other.
However, when a semiconductor device is constituted by connecting heterogeneous chips to each other using a connecting conductor which passes through a substrate, a connecting hole has to be opened while securing insulation of a deep substrate. Thus, practical usage is difficult due to a cost economy of a manufacturing process necessary for processing a connecting hole and embedding a connecting conductor.
On the other hand, it is necessary to thin an upper chip to an utmost limit to form, for example, a small contact hole of about 1 μm. In this case, a complicated step such as bonding the upper chip to a supporting substrate before the thinning or the like is necessary, and a manufacturing cost is increased, in addition, since it is necessary to use a chemical vapor deposition (CND) film having good coatability such as tungsten (W) as a connecting conductor to embed the connecting conductor in a connecting hole of a high aspect ratio, a material of the connecting conductor is limited.
Thus, a method of manufacturing a semiconductor device such as a solid-state imaging device in which each performance is sufficiently secured, high performance is attained, and mass production and cost reduction are attained (for example, refer to Patent Literature 1).
In Patent Literature 1, realization of a stacked structure by stacking a supporting substrate of a rear surface type image sensor as a logic circuit and providing a plurality of connecting contacts from an upper portion using a step of thinning the image sensor is proposed.
However, in recent years, a three-layer-stacked solid-state imaging device has also been proposed. When a stacked image sensor is constituted as a three-layer-stacked structure, it is necessary for a sensor having a light-receiving part to capture light. Thus, since the sensor is disposed at an uppermost portion, two chips are stacked as lower layers thereof n this case, for example, a logic chip, a memory chip, or the like can be used as the two chips serving as the lower layers.
Generally, it is desirable that a supporting substrate is not used to thin a silicon substrate when a circuit is stacked. In this case, in producing a circuit, circuit surfaces of two chips serving as lower layers are first bonded to face each other, and a chip of a second layer is thinned. After that, a sensor of an uppermost layer is bonded and stacked as a rear surface type, and the chip is further thinned.
Accordingly, however, the following problem occurs in a three-layer-stacked structure. In other words, a pad opening to a pad metal unnecessarily becomes too deep. In other words, since an opening is provided up to an A1 layer of a chip of a second layer, the opening has to pass through a sensor of a chip of an uppermost layer, pass through a silicon substrate of the chip of the second layer, and reach the A1 layer in the lowermost layer of a wiring layer. Thickening a resist as well as curing a resist after dry etching is a problem in opening a deep pad.
For example, since an organic lens is already formed on a chip at a time of opening, a resist has to be removed using a chemical solution. However, the cured resist easily remains on a residue and thus inhibits incident light on the lens. Deposits generated due to dry etching are also a problem. In particular, deposits, which adhere to and are not removed from a metal surface of a pad and sidewalls of a pad opening, generate fluorine ions by absorbing moisture after a chip is completed and cause a failure in which a metal of a pad is melted (corroded). As described above, a process becomes difficult due to a deeper pad.
Also, in a pad opening region in a second layer or a subsequent layer, it has so far been necessary to form a through opening in a stacked product. Thus, a wiring or a circuit element cannot be disposed and a lot of dead space is generated. A measuring task for an evaluation item in which an upper substrate is not originally necessary has to be performed after all stackings have been completed, and a task such as discarding a defective wafer or redundancy repair is performed on a completely stacked product. Therefore, a defect rate is increased or a measurement time is increased.